The present invention generally relates to semiconductor devices and more particularly to a fabrication process of a semiconductor device having a multilayer interconnection structure that uses a low-dielectric organic spin-on insulation film for an interlayer insulation film.
In the art of high-resolution lithography, leading-edge semiconductor integrated circuit devices include an enormous number of semiconductor devices on a substrate. In such advanced semiconductor integrated circuit devices, the use of a single interconnection layer is not sufficient for interconnecting the semiconductor devices on the substrate, and it is common to provide a multilayer interconnection structure on the substrate, wherein a multilayer interconnection structure includes a plurality of interconnection layers stacked with each other with intervening interlayer insulating films.
Particularly, there is an intensive effort made with regard to the so-called dual-damascene process in the art of multilayer interconnection structure in which a typical dual-damascene process includes the steps of forming grooves and contact holes in an interlayer insulating film in correspondence to the interconnection patterns to be formed, and filling the grooves and the contact holes by a conducting material to form the desired interconnection pattern.
While there exist various modifications in the dual-damascene process, the processes in FIGS. 1A-1F represent a typical conventional dual-damascene process used for forming a multilayer interconnection structure.
Referring to FIG. 1A, a Si substrate 10, carrying thereon various semiconductor device elements such as MOS (Metal-Oxide-Silicon) transistors not illustrated, is covered by an interlayer insulating film 11 such as a CVD (Chemical Vapor Deposition)-SiO2 film, and the interlayer insulating film 11 carries thereon an interconnection pattern 12A. It should be noted that the interconnection pattern 12A is embedded in a next interlayer insulating film 12B formed on the interlayer insulating film 11, and an etching stopper film 13 of SiN, and the like, is provided so as to cover the interconnection pattern 12A and the interlayer insulating film 12B forming an interconnection layer 12. The etching stopper film 13, in turn, is covered by another interlayer insulating film 14, and the interlayer insulating film 14 is covered by another etching stopper film 15.
In the illustrated example, there is a further interlayer insulating film 16 formed on the etching stopper film 15, and the interlayer insulating film 16 is covered by a next etching stopper film 17. The etching stopper films 15 and 17 are also called as “hard mask.”
In the step of FIG. 1A, a resist pattern 18 is formed on the etching stopper film 17 with a resist opening 18A formed in correspondence to a desired contact hole by a photolithographic patterning process, and the etching stopper film 17 is removed by a dry etching process while using the resist pattern 18 as a mask. As a result, there is formed an opening corresponding to the desired contact hole in the etching stopper film 17.
Next, in the step of FIG. 1B, the interlayer insulating film 16 underlying the etching stopper film 17 is subjected to a reactive ion etching (RIE) process, and an opening 16A is formed in the interlayer insulating film 16 in correspondence to the desired contact hole. Further, the resist pattern is removed. In the case the interlayer insulation film 16 is an organic film, the resist pattern is removed simultaneously to the step of etching the interlayer insulation film 16 to form the contact hole 16A.
Next, in the step of FIG. 1C, a resist film 19 is formed on the structure of FIG. 1B, and the resist film 19 is patterned subsequently in the step of FIG. 1D by a photolithographic patterning process so as to form a resist opening 19A corresponding to a desired interconnection pattern. As a result of the formation of the resist opening 19A, the opening 16A in the interlayer insulating film 16 is exposed.
In the step of FIG. 1D, the etchings stopper film 17 exposed by the resist opening 19A and the etching stopper film 15 exposed at the bottom of the opening 16A are removed by a dry etching process while using the resist film 19 as a mask, and the interlayer insulating film 16 and the interlayer insulating film 14 are patterned simultaneously in the step of FIG. 1E. As a result of the patterning, there is formed a opening 14A corresponding to the desired interconnection groove in the interlayer insulating film 16. The opening 16B is formed so as to include the opening 16A.
Next, in the step of FIG. 1F, the etching stopper film 13 exposed at the contact hole 14A is removed by an RIE process, causing exposure of the interconnection pattern 12A. After this, the interconnection groove 16A and the opening 14A are filled with a conductor layer such as an Al layer or a Cu layer, wherein the conductor layer is subsequently subjected to a chemical mechanical polishing (CMP) process, to form an interconnection pattern 20 in electrical contact with the underlying interconnection pattern 12A via the contact hole 14A. Interconnection patterns of third and fourth layers can be formed similarly by repeating the foregoing process steps.
Meanwhile, conventional semiconductor devices have achieved large integration density and high performance by miniaturizing the design rule. However, the use of strict design rules invite the problem of increased interconnection resistance and inter-wiring capacitance, and there is emerging a situation in which further improvement of performance is difficult as long as conventional interconnection material is used. Thus, investigations are being made with regard to the use of low-resistance Cu for the interconnection material and further with regard to the use of low-dielectric material for the interlayer insulation film so as to reduce the interconnection capacitance.
Particularly, recent advanced semiconductor integrated circuits tend to construct the multilayer interconnection structure by using Cu having a characteristically low resistance as the material of the interconnection pattern in place of conventionally used Al, in combination with a low-dielectric interlayer insulation film, by way of a damascene process.
In view of the fact that the dual damascene process explained before includes a CMP process, the low-dielectric material used in such a dual damascene process is required to have an excellent mechanical property with regard to shear and compressive stress, and hence adhesion, in addition to the required small inter-wiring capacitance. This mechanical strength is one of the most important factors required for a low-dielectric insulation film used in a dual damascene process.
In the event SiO2 or BPSG is used for the interlayer insulating film as in the case of conventional multilayer interconnection structures, it should be noted that the specific dielectric constant of the interlayer insulating film generally takes a value of 4-5. This value of the specific dielectric constant can be reduced to 3.3-3.6 by using a F (fluorine)-doped SiO2 film called FSG. Further, the value of the specific dielectric constant can be reduced 2.9-3.1 by using an SiO2 film having a Si—H group in the structure thereof such as an HSQ (hydrogen silsesquioxane) film. Further, the use of an organic SOG or organic insulating film is proposed. In the case an organic SOG is used, it becomes possible to reduce the specific dielectric constant to below 3.0. Further, the use of an organic insulating film can realize a still lower specific dielectric constant of about 2.7.
These low-dielectric interlayer insulation films of organic family can be formed either by a pyrolytic CVD process or a plasma CVD process or a spin-on process, wherein the spin-on process has a distinct advantage of large degree of freedom in choosing the solution forming the insulating material over the CVD process, in addition to the advantage of large throughput.
Normally, a spin-coating process starts with a step of setting a silicon substrate on a spin coater and causing a solution to form a film of the low-dielectric interlayer insulation material of organic family on the silicon substrate while spinning the substrate. The silicon substrate is then subjected to a drying process for evaporating the solvent from the film, and a curing process is applied in a heat treatment apparatus, which may be selected from a hot plate, a furnace or a lamp according to the need. As a result of the final thermal curing process, a solvent-insoluble, highly cross-linked insulation film is obtained.
In the case of forming a multilayer interconnection structure by a dual damascene process while using low-resistance Cu, it is important to use a CMP process in view of the difficulty of applying a dry etching process to Cu. In relation to the use of the CMP process, there arises a problem, particularly when an organic insulation film is used, in that the organic insulation film has a poor adhesion characteristic.